1. Field of the Invention
The invention pertains generally to methods for fabricating semiconductor devices, e.g., semiconductor integrated circuit (IC) devices, as well as the resulting devices.
2. Art Background
Semiconductor ICs are devices which include a plurality of electrically interconnected discrete devices formed in and on a semiconductor substrate. Included among these ICs are MOS (metal-oxide-semiconductor) and MES (metal-semiconductor) ICs. The MOS ICs typically include a plurality of MOSFETs (MOS field effect transistors), each of which includes an active surface layer of semiconductor material, e.g., silicon. Each MOSFET also includes a relatively thin gate oxide (GOX) formed on the surface of the active layer, a gate electrode of, for example, polycrystalline silicon (polysilicon), formed on the surface of the GOX, and two relatively heavily doped portions of the active layer, on opposite sides of the gate electrode, which constitute the source and drain of the MOSFET. A relatively thick (compared to the GOX) field oxide (FOX) serves to separate and electrically insulate the MOSFETs from one another. Similarly, the MES ICs typically include a plurality of MESFETs (MES field effect transistors), with the MESFETs differing from MOSFETs only in that the MESFET gate electrodes are of metal or of a metal-containing compound, e.g., a metal silicide, and directly contact the semiconductor material.
At present, in commercially available ICs, the length of the gate electrode, and thus the length of the current channel, is typically about 2 micrometers (.mu.m), while the depth of both the source and drain is typically about 0.5 .mu.m. However, to achieve ICs having increased packing densities (of discrete devices), it is expected that gate electrode lengths (and thus current channel lengths) will be reduced to values equal to or less than about 1 .mu.m. Concomitantly, to avoid certain undesirable effects, usually termed short-channel effects, it is also expected that the depths of the sources and/or drains will be reduced to values equal to or less than about 0.2 .mu.m. (The undesirable short-channel effects, referred to here, are unwanted threshold voltage shifts and source-to-drain subthreshold leakage currents which occur when the ratio of channel length to source/drain depth is relatively small, e.g., equal to or less than about 2.5. Regarding short-channel effects see, e.g., J. R. Brews et al, "Generalized guide for MOSFET miniaturization," IEEE Elect. Dev. Lett., Vol. EDL-1(1), p. 2, (1980).)
Significantly, relatively shallow sources and drains, i.e., sources and drains having depths equal to or less than about 0.2 .mu.m, exhibit undesirably large resistances, which adversely affect device performance. To achieve relatively low source/drain resistance while employing relatively shallow sources and drains, it has been proposed that each relatively shallow source and drain be formed to include an overlying region of metal silicide, e.g., molybdenum silicide (MoSi.sub.2), tungsten silicide (WSi.sub.2), or titanium silicide (TiSi.sub.2), the purpose of which is to serve as a low-resistance current shunt. In this regard, the effective (electrical) depth of a metal silicide-covered source or drain, i.e., the depth involved in source-drain-gate interactions, is the combined depth of the metal silicide region and the underlying (heavily doped) source or drain as measured relative to, and extending beneath, the surface of the active layer.
Previous attempts to fabricate ICs containing metal silicide-covered sources and drains have involved the use of conventional procedures for forming sources and drains, i.e., have involved implanting and diffusing source/drain dopant into those regions of a silicon substrate where the sources and drains are desired, followed by deposition of a metal, such as Mo, W and Ti, onto the surfaces of the underlying sources and drains. The deposited metal was then reacted with the underlying silicon of the sources and drains (thus consuming some of the silicon) to form the corresponding metal silicide. This technique has proven effective in those cases where the sources and drains initially (prior to the formation of the metal silicide) extended relatively deeply into the silicon, i.e., extended more than about 0.25 .mu.m into the silicon. However, this technique has proven undesirable in those cases where the sources and drains initially extended only a relatively small distance into the silicon, i.e., extended by a distance equal to or less than about 0.25 .mu.m, because, among other reasons, an undesirably large amount of source/drain silicon was consumed in forming the metal silicide, resulting in metal silicide spikes extending through, and thus short-circuiting, the source/drain p-n junctions.
A different technique for forming metal silicide-covered sources and drains is described by H. Okabayashi et al in "A New Low Resistance Shallow Junction Formation Method Using Lateral Diffusion Through Silicide," IEDM Technical Digest, pp. 670-673 (1983). In accordance with this technique, such a source or drain is formed by initially fabricating a region of molybdenum silicide (MoSi.sub.2) having a thickness of, for example, 0.1 .mu.m, on the surface of a silicon substrate. This is achieved by depositing molybdenum onto the silicon substrate and reacting the molybdenum with the underlying silicon. Then, source/drain dopant is diffused into the molybdenum silicide, from which it is diffused into the underlying silicon to form the source/drain p-n junction. That is, the molybdenum silicide-covered silicon substrate is contacted by a gaseous or solid dopant source while heated to a sufficiently high temperature and for a sufficiently long time period, e.g., 1000 degrees Centigrade (C) and 20 minutes, to effect dopant diffusion into the molybdenum silicide and then into the underlying silicon, in one step. Alternatively, the dopant is diffused into the silicon in a two-step process, the first step being to diffuse the dopant from the gaseous or solid dopant source into the molybdenum silicide (but not into silicon) by initially heating the molybdenum silicide-covered silicon substrate to a relatively low temperature, e.g., 800 degrees C. Subsequently, dopant is diffused out of the molybdenum silicide and into the silicon by heating the substrate to a substantially higher temperature, e.g., 950 or 1000 degrees C. Significantly, the one-step diffusion process yields relatively deep sources and drains, e.g., if the molybdenum silicide is 0.1 .mu.m thick, then the source or drain extends about 1.5 .mu.m below the upper surface of the silicide. While the two-step diffusion process yields shallower sources and drains, they are also relatively deep, e.g., if the molybdenum silicide is 0.1 .mu.m thick, then the source or drain extends about 0.36 .mu.m below the upper surface of the silicide.
In yet another technique previously used to form metal silicide-covered sources and drains, a region of tungsten silicide (WSi.sub.2) is initially formed on a silicon substrate, and dopant is implanted (rather than diffused) into the tungsten silicide. (See F. C. Shone et al, "Formation of 0.1 .mu.m N.sup.+ /P and P.sup.+ /N Junctions by Doped Silicide Technology," IEDM Technical Digest, pp. 407-410 (1985).) Then, the implanted dopant is diffused out of the tungsten silicide and into the silicon substrate by heating the substrate, using either conventional furnace annealing techniques or rapid thermal annealing (RTA) techniques. (Regarding RTA see, e.g., T. O. Sedgwick, "Short Time Annealing", Journal of the Electrochemical Society, Vol. 130, p. 484 (1983).) Significantly (as taught in F. C. Shone et al, supra), the thickness of the tungsten silicide region is 0.2 .mu.m, and the corresponding implant doses, heating temperatures and heating times are all (presumably) specifically tailored to this particular thickness of tungsten silicide. As a result, this particular technique only yields sources and drains having depths (as measured from the upper surface of the tungsten silicide) equal to or greater than 0.3 .mu.m.
A variant of the above technique is described by N. Kobayashi et al in "Comparison of TiSi.sub.2 and WSi.sub.2 Silicided Shallow Junctions For Sub-Micron CMOSs," Digest of papers, 1986 Symposium on VLSI Technology, San Diego (1986). Here, a 0.1 .mu.m-thick region of either tungsten silicide or titanium silicide is initially formed on a silicon substrate, source/drain dopant is implanted into the silicide and then diffused out of the silicide and into the silicon. However, in the case of tungsten silicide, and as shown in FIG. 1 of the N. Kobayashi et al journal article, the authors of the article teach implant doses, heating temperatures and heating times which yield sources and drains having depths (as measured from the upper surface of the tungsten silicide) significantly greater than 0.2 .mu.m, e.g., depths of 0.26 .mu.m and 0.28 .mu.m. By contrast, in the case of titanium silicide, and as shown in FIG. 1, the authors do teach an arsenic implant dose, heating temperature and heating time which yields a source or drain having a depth (as measured from the surface of the titanium silicide) which is less than 0.2 .mu.m, i.e., about 0.16 .mu.m. But, as is also evident from FIG. 1, the concentration of arsenic at the titanium silicide/silicon interface is relatively low. This is highly significant because (contrary to the assertions made by the authors of the journal article) this relatively low interface concentration leads to an undesirably high specific contact resistance (R.sub.c), i.e., an R.sub.c substantially higher than 10.sup.-6 .OMEGA.-cm.sup.2. In fact, in the journal article, the authors indicate the desirability of implanting additional arsenic into the silicon (not into the titanium silicide) in order to increase interface arsenic concentration (presumably for the purpose of lowering R.sub.c). Unfortunately, as is known, such a procedure is undesirable because the silicon substrate must then be heated to a relatively high temperature to anneal out the resulting implant damage in the silicon, which produces additional dopant diffusion and, as a consequence, relatively deep sources and drains.
Thus, those engaged in the development of IC fabrication methods have sought, thus far without success, methods for fabricating ICs having metal silicide-containing, relatively shallow sources and drains exhibiting R.sub.c s equal to or less than about 10.sup.-6 .OMEGA.-cm.sup.2.